A static random access memory (SRAM) is a significant memory device due to its high speed, low power consumption, and simple operation. Unlike a dynamic random access memory (DRAM) cell, the SRAM does not need to regularly refresh the stored data and it has a straightforward design.
Each bit in a typical six-transistor SRAM (6T-SRAM) cell is stored on four transistors, generally referred to as load transistors (or pull-up transistors) and driver transistors (or pull-down transistors), that form a flip-flop circuit containing two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors (or pass-gate transistors) serve to control the access to a storage cell during read and write operations.
To function properly, the SRAM cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell, the cell current generated as the pass-gate transistor turns ‘on’ must not flip the voltage level at the internal cell nodes. To stabilize the cell, the driver or pull-down transistor is fabricated to have a higher conductance than the pass-gate transistor.
The ratio of the conductance of the pull-down transistor over the conductance of the pass-transistor therefore can be used as a basic metric to measure the stability of the SRAM cell or the ability of the cell to retain its data state. This conductance ratio is generally referred to as “beta ratio.” The larger the beta ratio, the more stable the SRAM cell. Depending on the SRAM application, the beta ratio is typically at least about 1.5, and preferably ranges from about 1.8 to about 3.
The conductance of a transistor is approximately proportional to the effective carrier mobility μeff and the ratio of the device width to the channel length, i.e., W/L. Accordingly, the beta ratio of the SRAM cell can be approximated by the ratio of μeff(W/L) of the pull-down transistor over μeff(W/L) of the pass-gate transistor. Usually, the beta ratio of a SRAM cell is controlled by adjusting the W/L of the pull-down transistor relative to that of the pass-gate transistor. If the pull-down and the pass-gate transistors have the same channel length and effective carrier mobility, as in most cases, then the beta ratio becomes the ratio of the channel width of the pull-down transistor over the channel width of the pass-gate transistor.
Therefore, in most SRAM cells, the pull-down transistors are fabricated with a channel width that is approximately twice as large as that of the pass-gate transistors.
FIG. 1 presents a top-down view of an exemplary SRAM cell layout, which contains the active regions, isolation regions, gate structures, and contact structures that may be used to form the typical metal oxide semiconductor (MOS) transistors in a typical complementary metal oxide semiconductor (CMOS) SRAM cell. Specifically, pass-gate transistors 1 and 4 and pull-down transistors 2 and 3 are formed within connected active regions 12 and 14 (i.e., there is no isolation between the active region of the pass-gate transistor 1 or 4 and the active region of the pull-down transistor 2 or 3), and pull-up transistors 5 and 6 are formed within active regions 16 and 18. The active regions 12, 14, 16, and 18 are formed within a semiconductor substrate, which may preferably be a silicon substrate doped with n-type and p-type impurities in the vicinity of the p-channel transistors and the n-channel transistors, respectively, and are separated from one another by dielectric isolation regions 31-33. Gate structures 22 and 26 are arranged above active region 12 to form gates of pull-down transistor 2 and pass-gate transistor 1, respectively. Similarly, above active region 14, gate structures 24 and 28 are arranged to form gates of pull-down transistor 3 and pass-gate transistor 4, respectively. Consequently, active regions 16 and 18 each have two gate structures 22 and 24 arranged above them.
In FIG. 1, the active region 12 that forms the pass-gate transistor 1 and the pull-down transistor 2 has a first width W1 at a first region 12a, and a second width W2 at a second region 12b, while W1 is approximately only half of W2. Similarly, the active region 14 that forms the pull-down transistor 3 and the pass-gate transistor 4 also has a narrow region 14a of width W1 and a wide region 14b of width W2. In such a manner, the active regions of the pull-down transistors 2 and 3 are about twice as large as the active regions of the pass-gate transistors 1 and 4, thereby enhancing the beta ratio and ensuring the stability of the SRAM cell.
Note that in each of the connected active regions 12 and 14, a transition region exists between the narrow region and the wide region of the respective connected active region, where the device width changes drastically.
Advanced lithography is usually used for fabricating SRAM cells, due to the dimensional scalability provided by lithography technology. However, although advanced lithography is very effective for manufacturing device features of regular size, the transition region between the narrow region and the wide region of the connected active region of the SRAM cell presents a challenge to the lithography process. Consequently, the processing complexity and manufacturing costs for the SRAM cells increase significantly due to the presence of such a transition region.